1. Field of the Invention
The present invention relates to a low divide ratio programmable frequency divider of a fractional-N type applied to a digital Mixer Oscillator Phaselocked Loop (MOPLL) tuner and a method thereof. More particularly, the present invention relates to a low divide programmable frequency divider which can operate at a higher comparison frequency with a lowered main divide ratio, and thereby can be improved in phase noise properties and scaled down.
2. Description of the Related Art
In general, for a frequency synthesizer generating an oscillation frequency Fvco, a variable oscillator and a Phase Locked Loop (PLL) are employed. The variable oscillator multiplies, diminishes or mixes the oscillation frequency based on a highly stable crystal oscillator (X-tal) to oscillate a predetermined frequency. The PLL controls a phase of the variable oscillator.
FIG. 1 is a sectional view of a frequency synthesizer according to the prior art.
The conventional frequency synthesizer shown in FIG. 1, when applied to a digital MOPLL tuner, includes a plurality of mixers M1-M3 for mixing input signals SL, SM and SH including VHF-L, VHF-H and UHF bands with oscillation frequencies to output an intermediate frequency signal IFout, a plurality of oscillators VCO1-VCO3 for providing the oscillation frequencies to the mixers M1-M3, and a multiband PLL 10 for controlling each of the oscillators VCO1-VCO3.
When employed in the digital MOPLL tuner for receiving a digital TV signal, such a frequency synthesizer is required to have a high channel selectivity within a range that satisfies noise properties such as phase noise and sideband spurious in consideration of channel spacing.
The PLL used for the frequency synthesizer is largely broken down into an integer-N PLL and a fractional-N PLL. In particular, advantageously, the fractional-N PLL exhibits low phase noise properties.
Characteristically, the fractional-N PLL entails fractional spurious necessarily. In the most widely-known noise shaping method for inhibiting such fractional spurious, a discrete sigma-delta (Σ□) modulator is adopted. The sigma-delta modulator shifts fractional spurious out of a loop bandwidth of the PLL in converting a low frequency noise into a high frequency noise.
To employ the sigma-delta modulator requires a divide ratio which varies more frequently within a broad variable range per divide cycle.
Of the conventional PLLs, the sigma-delta modulation-based factional-N PLL will be explained hereunder with reference to FIGS. 2 to 4.
FIG. 2 is a configuration view illustrating a factional-N PLL using a third-order sigma-delta modulation of the prior art.
The conventional fractional-N PLL shown in FIG. 2 includes a reference divider 22 for dividing a reference frequency Fref from a reference frequency generator 21 by a reference divide ratio, a programmable frequency divider 23 for varying the divide ratio in response to a control signal inputted and dividing an oscillation frequency Fvco of a voltage control oscillator VC0 by the varied divide ratio, a phase difference detector 24 for detecting a phase difference between a comparison frequency Fc divided by the reference divider and a divide oscillation frequency Fv divided by the programmable frequency divider 23, a charge pump 25 for pumping a charge according to the phase difference from the phase difference detector 24 and supplying a voltage corresponding to the phase difference; and a low-pass filter 26 for low-passing the voltage from the charge pump 25 to stabilize and then supplying the same to the voltage control oscillator VCO as a tuning voltage VT.
Further, the frequency synthesizer employs a third-order sigma-delta modulator 27 which provides divide data to the programmable frequency divider 23 to vary the divide ratio. The third-order sigma-delta modulator 27 including an M bit accumulator inside receives K[M bit] corresponding to the numerator of the fractional section in fraction-N divide ratio (FN=N+K/2M), and accumulates the K. At this time, the third Σ␣ modulator 27 generates carry in case where the accumulated value exceeds the denominator (2M). Then the third Σ□ modulator 27 outputs the resultant carry (Σ□) and integer divide ratio N to the programmable frequency divider 23 as the divide data.
FIG. 3 is a configuration view illustrating the programmable frequency divider of FIG. 2.
Referring to FIG. 3, the programmable divider 27 includes a prescaler 31, a main counter and a pulse swallow counter 33.
The prescaler 31 includes a variable divider 31a for dividing by 4 or 5 as pre-set in response to a swallow control signal SC, a double counter 31b for double-counting a frequency from the variable divider 31a to divide by 2, an output selector 31c for selecting the frequency Fvco/4 or Fvco/5 divided by 4 or 5 by the variable divider 31a or the frequency double-counted by the double counter 31c in response to a mode selection signal SEL8, a level converter 31d for converting an output frequency level of the output selector 31c into a full-swing level, and a pulse swallow controller 31e for out putting the swallow control signal SC to the variable divider 31c in response to an output signal PO from the level converter 31c and a swallow signal SW from the pulse swallow counter 33.
The main counter 32 divides the frequency divided by the prescaler 31 by a pre-set main divide ratio M to generate a divide oscillation frequency Fv. The pulse swallow counter 33 counts a clock from the main counter 32 and outputs “0” during the counting. Then, if a counting value corresponds to a pre-set pulse swallow value S, the pulse swallow counter 33 outputs the pulse swallow signal SW of “1” to the pulse swallow controller 31e of the prescaler 31.
This conventional programmable frequency divider operates on a divide-by-4/5 mode or a divide-by-8/9 mode in response to the mode selection signal SEL8. Also, the divide ratio in each mode varies in response to the pulse swallow signal SW, which will be explained with reference to FIGS. 4a and 4b. 
FIGS. 4a and 4b are flowcharts illustrating operation of the programmable frequency divider of FIG. 3.
First, with reference to FIG. 4a, an explanation will be given regarding a divide-by-4/5 mode in which the prescaler 31 divides the oscillation frequency Fvco by 4 or 5.
Referring to FIG. 4a, if the prescaler 31 divides the oscillation frequency Fvco by 4 or 5 in response to the pulse swallow signal SW of the pulse swallow counter 33, in case of the divide ratio of 1 byte (8bit:b8b7b6b5 b4b3b2b1), lowest 2 bits b2mb1 are assigned as the pulse swallow value S and the other bits (b8b7b6b5 b4b3) are assigned as the main divide ratio M. Herein, the prescaler executes a pulse swallow if the main divide ratio M corresponds to the pulse swallow value S. Therefore, the pulse swallow value S cannot be bigger than the main divide ratio M. In addition, a sigma-delta-induced negative number should be considered.
In this regard, a minimum divide ratio in the divide-by-4 or 5 mode is 20(0001 0100). At this time, a VCO output frequency is produced with each different reference frequency applied, at the minimum divide ratio according to following equation 1.rm Fvco=Fref*FN   Equation 1
According to equation 1, in case where the divide ratio FN is 20 and the reference frequencies Fref are 4 MHz, 8 MHz and 16 MHz, the oscillation frequencies Fvco are 80 MHz (4 MHz*20), 160 MHz (8 MHz*20) and 320 MHz (16 MHz*20), respectively.
Then, with reference to FIG. 4b, an explanation will be given regarding a divide-by-8/9 mode in which the prescaler 31 divides the oscillation frequency Fvco by 8 or 9.
Referring to FIG. 4b, if the prescaler 31 divides the oscillation frequency Fvco by 8 or 9 in response to the pulse swallow signal SW of the pulse swallow counter 33 and the double counter, in case of the divide ratio of 1 byte (8 bits: b8b7b6b5 b4b3b2b1), lowest 3 bits (b3b2b1) are assigned as the pulse swallow value S and the other bits (b8b7b6b5 b4) are assigned as the main divide ratio M. Herein, as described above, the pulse swallow value S cannot be bigger than the main divide ratio M. Also, a sigma-delta-based negative numeral should be considered.
In this regard, the minimum divide ratio in a divide-by-8 or 9 mode is 72(0100 1000). At this time, the VCO output frequency is produced with each different reference frequency applied, at the minimum divide ratio according to aforesaid equation 1. According to equation 1, in case where the divide ratio FN is 72 and the reference frequencies Fref are 4 MHz, 8 MHz and 16 MHz, the oscillation frequencies Fvco are 288 MHz (4 MHz*72), 576 MHz (8 MHz*72) and 1152 MHz (16 MHz*72), respectively.
However, this conventional programmable frequency divider disadvantageously cannot employ a high reference frequency Xtal in the factional-N PLL directed at miniaturization and low phase noise.
As a result, the main counter should be assigned with a high main divide ratio, thus leading to degradation in phase noise properties and limitations in scaling down a reference frequency generator.